1. Field of the Invention
The present invention relates to a method of making a semiconductor assembly and a semiconductor assembly manufactured thereby, and more particularly to a method of making a semiconductor assembly with semiconductor device in a cavity defined by a bump/flange sacrificial carrier and a semiconductor assembly manufactured thereby.
2. Description of Related Art
Latest trends of electronic devices such as mobile internet devices (MIDs), multimedia devices and computer notebooks demand for faster and slimmer designs. In the frequency band of a general signal, the shorter paths of circuitry, the better the signal integrity. Thus, the size of inter-layer connection, i.e., the diameter of the micro-via and plated through hole in the substrate must be reduced in order to improve the signal delivery characteristic of the electronic component. As plated-through-hole in the copper-clad laminate core is typically formed by mechanical CNC drill, reducing its diameter in order to increase wiring density may encounter seriously technical limitations and often very costly. As such, coreless substrates are proposed for packaging substrate to enable a thinner, lighter and faster design of the components. However, as coreless boards do not have a core layer to provide a necessary flexural rigidity, they are more susceptible to warpage problem when under thermal stress compared to that of conventional boards with core layers.
U.S. Pat. No. 7,164,198 to Nakamura et al., U.S. Pat. No. 7,400,035 to Abe et al., U.S. Pat. No. 7,582,961 to Chia et al., U.S. Pat. No. 7,934,313 to Lin et al. disclose a coreless packaging substrate with built-in stiffener by etching a portion of a metal sheet on which the build-up circuitry is formed. The built-in stiffener defines a cavity which serves as the region for semiconductor device attachment. In this approach, although a supporting platform can be created and warping issues may be improved, etching a thick metal block is prohibitively cumbersome, low throughput, and prone to create many yield-loss issues such as an uncontrollable boundary line due to etching under-cut.
U.S. Pat. No. 8,108,993 to Higashi et al. discloses a method to form built-in stiffener by using a supporting substrate on which the build-up circuitry is formed. In this approach, a peeling promotion layer is applied on the supporting substrate so that the build-up layers can be separated from the supporting substrate after the coreless wiring board is finished. Since the peeling promotion layer, either a thermal setting resin or an oxide film, has the peeling off property when under a heat or light treatment, there exists a high risk of early delamination during dielectric layer coating and curing, this may result in serious yield and reliability concerns.
In view of the various development stages and limitations in currently available coreless substrate for high I/O and high performance semiconductor devices, there is a need for a packaging technique that can provide optimize signal integrity, maintain low warping during assembly and operation, and low cost manufacturing.